1. Technical Field
Various embodiments relate generally to an electronic device.
2. Related Art
As integration of a semiconductor device increased, the size of a memory cell decreased, and as a result, the level of difficulty with a manufacturing process increased. Recently, due to the limit in increase in integration of a 2-dimensional (2D) semiconductor device having a channel arranged horizontal to a semiconductor substrate, a 3-dimensional (3D) semiconductor device having a vertical channel is proposed.
A memory cell array of the 3D semiconductor device includes a plurality of memory blocks. Each of the memory blocks includes a plurality of cell strings disposed vertically relative to a surface of a semiconductor substrate. More specifically, the cell strings include a vertical channel formed in a vertical direction to the surface of the semiconductor substrate, a drain selection transistor, memory cells, and a source selection transistor. The drain selection transistor, the memory cells, and the source selection transistor are formed along the vertical channel.
Since the cell strings of the 3D semiconductor device having the vertical channel have heights greater than those of the cell strings of the 2D semiconductor device, a structure of peripheral circuits configured to program read and erase the memory cells may be modified according to the structure change of the cell strings from 2D to 3D.
The peripheral circuits receive a power voltage, a ground voltage or other various voltage levels through a voltage line or a ground line, and operate based on various control signals output from a control circuit. In particular, among the peripheral circuits, page buffers coupled to the cell strings through bit lines include a plurality of elements such as a latch, a precharge switch and a discharge switch. Among the elements, switching elements configured to transmit the power voltage, the ground voltage or the voltages of various levels may malfunction when the voltage is supplied properly, thereby deteriorating reliability of the semiconductor device.